Tuning for Cryptographic Hashing Algorithms

The main reason I haven't written in awhile is that I've been working on a paper on performance tuning for cryptographic hashing algorithms, which is finally done. This paper investigates processor configurations optimal for RIPEMD-160, SHA-1, and MD5 algorithms. It provides detailed information on CPU design, cache organization, and compiler optimizations for each of the algorithms, and draws some conclusions on the cryptographic hashing application domain as a whole. The data is also available on my website. This information would be helpful to an engineer desinging an FPGA for hardware-accelerated hashing, and could also be of use in choosing a general-purpose CPU that would be performing intensive cryptographic hashing. There is certainly more to explore than what the paper covers, but it gives a good overview of the demands placed on hardware by these algorithms and opportunities for better efficiency.

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